Often, hardware configurations for reconfigurable computing systems are designed for a specific single application or a cooperating set of behaviors to run at one time on the reconfigurable computing system. And although a particular application's configuration may contain multiple hardware functions, the configuration is not usually designed to allow different unrelated applications to simultaneously share a single reconfigurable computing Field Programmable Gate Array (“FPGA”) level resource. The ability for a single configuration file to contain multiple independent hardware objects that interface to multiple application programs running simultaneously on a host system is increasingly important as reconfigurable computing technology migrates to mainstream and special purpose high performance computing environments.
Methods disclosed in U.S. Pat. No. 6,539,438, assigned to common assignee QuickFlex, Inc. and which is herein incorporated by reference, address a means for making reconfigurable computing resources dynamically reprogrammable from application software instances. This patent discloses a means by which middleware can provide access from multiple simultaneously executing software applications to one or more reconfigurable computing resources, each reconfigurable computing resource hosting one or more hardware behaviors that may be loaded dynamically.
Further, some currently available FPGA devices support configuration functionality known as partial dynamic reconfiguration. Partial dynamic reconfiguration makes it possible to load hardware behaviors into a portion of the FPGA while the remainder of the FPGA operates in normal functional (i.e., non-configuration) mode. The emergence of this technology enables the continuous exploitation of reconfigurable computing resources even while portions of those resources are being loaded with new hardware behaviors thereby improving both the flexibility and computational effectiveness of the underlying reconfigurable computing resource utilized in U.S. Pat. No. 6,539,438.
However, the partial dynamic reconfiguration capabilities currently available largely rely on the identification and usage of dedicated physical regions of the underlying FPGA device available for partial reconfiguration as a single operation. The location and structure of the boundaries of these regions must follow certain design rules to ensure that there is no electrical damage to the device as a result of temporary drive conflicts during reconfiguration. These rules vary from device family to device family, but generally are meant to ensure that no circumstance can arise during reconfiguration in which a single electrical network on the device has more than a single active driver.
A “bus macro” is a gate structure that, when used as a boundary to cordon off partially reconfigurable regions of an FPGA device, ensures that no drive conflicts or other potential sources of electrical damage to the device can occur during partial reconfiguration. These bus macro gate structures are placed at regular locations within the device and are typically found at the boundaries either of columns or banks—terms used for the individually addressable elements of the configuration fabric in FPGA devices (depending upon the device family).
As a result of the requirement to abide by the electrical rules needed to protect FPGA devices during partial dynamic reconfiguration, it becomes necessary to identify the specific regions that will be used for the partial dynamic reconfiguration. In practice, this has most often meant that at most one or two areas of the device are set aside for dynamic partial reconfiguration, with pre-determined, fixed boundaries—thus the usable region sizes are pre-set. Yet many applications and computing environments host hardware behaviors that may vary widely in both size and complexity, typically leading to highly inefficient use of the partially reconfigurable regions, with some behaviors requiring only a small percentage of the area available within a region.